Elpida EDJ1116EJBG Ficha Técnica descarregar pdf

Document. No. E1949E11 (Ver. 1.1)

Date Published September 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

©Elpida Memory, Inc. 2012

PRELIMINARY DATA SHEET

COVER

Specifications

• Density: 1G bits

• Organization

— 16M words × 8 bits × 8 banks (EDJ1108EJBG)

— 8M words × 16 bits × 8 banks (EDJ1116EJBG)

• Package

— 78-ball FBGA (EDJ1108EJBG)

— 96-ball FBGA (EDJ1116EJBG)

— Lead-free (RoHS compliant) and Halogen-free

• Power supply: 1.35V (typ)

— VDD = 1.283V to 1.45V

— Backward compatible for VDD, VDDQ

= 1.5V ± 0.075V

• Data rate

— 1866Mbps/1600Mbps/1333Mbps (max)

• 1KB page size (EDJ1108EJBG)

— Row address: A0 to A13

— Column address: A0 to A9

• 2KB page size (EDJ1116EJBG)

— Row address: A0 to A12

— Column address: A0 to A9

• Eight internal banks for concurrent operation

• Burst length (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

— Sequential (8, 4 with BC)

— Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13

• /CAS Write Latency (CWL): 5, 6, 7, 8, 9

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

— Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

— TC = 0°C to +95°C

Features

• Double-data-rate architecture: two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

— Synchronous ODT

— Dynamic ODT

— Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern

read out

• ZQ calibration for DQ drive and ODT

• /RESET pin for Power-up sequence and reset function

• SRT range:

— Normal/extended

• Programmable Output driver impedance control

• Seamless BL4 access with bank-grouping

— Applied only for DDR3-1333 and 1600

1G bits DDR3L SDRAM

EDJ1108EJBG (128M words × 8 bits)

EDJ1116EJBG (64M words × 16 bits)

1 2 3 4 5 6 ... 31 32

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Página 1 - 1G bits DDR3L SDRAM

Document. No. E1949E11 (Ver. 1.1)Date Published September 2012 (K) JapanPrinted in JapanURL: http://www.elpida.com©Elpida Memory, Inc. 2012PRELIMINAR

Página 2

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)101.4.1 Timings Used for IDD and IDDQ Measurement-Loop PatternsTable 5: Timings Us

Página 3

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)111.4.2 Basic IDD and IDDQ Measurement ConditionsTable 6: Basic IDD and IDDQ Measu

Página 4

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)12Notes: 1. Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0].2. MR: Mode Reg

Página 5 - EDJ1108EJBG, EDJ1116EJBG

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)13Notes: 1. DM must be driven low all the time. DQS, /DQS are MID-LEVEL.2. DQ sign

Página 6

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)14Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to re

Página 7

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)15Notes: 1. DM must be driven low all the time. DQS, /DQS are MID-LEVEL.2. DQ sign

Página 8

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)16Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to re

Página 9

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)17Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to wr

Página 10 - EDJ1108EJBG, EDJ1116EJBG

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)18Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to re

Página 11

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)192. Electrical Specifications2.1 DC CharacteristicsTable 15: DC Characteristics 1

Página 12

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)2Ordering InformationNote: 1. Please refer to the EDJ1108DJBG, EDJ1116DJBG datashe

Página 13

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)20Table 16: Self-Refresh Current (TC = 0°C to +85°C, VDD, VDDQ = 1.283V to 1.45V)P

Página 14

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)212.2 Pin CapacitanceNotes: 1. Although the DM, TDQS and /TDQS pins have different

Página 15

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)223. Absolute value of CCK-C/CK.4. Absolute value of CIO(DQS)-CIO(/DQS).5. CI appl

Página 16

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)232.3 Standard Speed BinsTable 19: DDR3-800 Speed BinsSpeed Bin DDR3-800ECL-tRCD-t

Página 17

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)24Table 21: DDR3-1333 Speed BinsSpeed Bin DDR3-1333HCL-tRCD-tRP 9-9-9Symbol /CAS w

Página 18

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)25Table 22: DDR3-1600 Speed BinsSpeed Bin DDR3-1600KCL-tRCD-tRP 11-11-11Symbol /CA

Página 19

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)26Table 23: DDR3-1866 Speed BinsSpeed Bin DDR3-1866MCL-tRCD-tRP 13-13-13Symbol /CA

Página 20

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)27Notes: 1. The CL setting and CWL setting result in tCK(avg)min and tCK(avg)max r

Página 21

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)283. Package Drawing3.1 78-ball FBGASolder ball: Lead free (Sn-Ag-Cu)7.50 ± 0.10IN

Página 22

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)293.2 96-ball FBGASolder ball: Lead free (Sn-Ag-Cu)7.50 ± 0.10INDEX MARK13.50 ± 0.

Página 23

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)3Pin ConfigurationsPin Configurations (×8 configuration)/xxx indicates active low

Página 24

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)304. Recommended Soldering ConditionsPlease consult with our sales offices for sol

Página 25

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)31NOTES FOR CMOS DEVICES1 PRECAUTION AGAINST ESD FOR MOS DEVICESExposing the MOS d

Página 26

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)32M01E1007No part of this document may be copied or reproduced in any form or by a

Página 27

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)4Pin Configurations (× 16 configuration)/xxx indicates active low signal.Notes: 1.

Página 28

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)5CONTENTSSpecifications ...

Página 29

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)61. Electrical Conditions• All voltages are referenced to VSS (GND)• Execute pow

Página 30

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)71.3 Recommended DC Operating ConditionsNotes: 1. Maximum DC value may not be grea

Página 31

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)81.4 IDD and IDDQ Measurement ConditionsIn this chapter, IDD and IDDQ measurement

Página 32

EDJ1108EJBG, EDJ1116EJBGPreliminary Data Sheet E1949E11 (Ver. 1.1)9Figure 2: Measurement Setup and Test Load for IDD and IDDQ MeasurementsFigure 3:

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